2D Radar on SoC-FPGA
- VHDL
- Nios II
- SoC-FPGA
- Avalon
- Quartus
- ModelSim
- VGA
- UART
- NeoPixel
Engineering mini-project completed at Polytech Sorbonne: design of a 2D mapping (radar) system combining an ultrasonic rangefinder and a servo motor, driven by a Nios II processor embedded on FPGA, with real-time display of the scanned scene.
Designed an ultrasonic rangefinder IP (HC-SR04 sensor) in VHDL: trigger pulse generation, echo duration measurement and conversion to distance, first validated in ModelSim simulation then tested standalone on FPGA (result shown on LEDs).
Designed a servo motor control IP generating a PWM signal (1 to 2 ms pulse every 10 to 20 ms) to precisely drive the scanning angle, validated in simulation then checked on an oscilloscope on the board.
Integrated both IPs as custom peripherals on the Avalon bus via Platform Designer, connected to a Nios II processor system.
Developed the embedded C application on the Nios II: distance acquisition (IORD), servo motor sweep over 180°, and scene mapping.
Real-time 2D map display on a VGA screen, and export of measurement data to a PC terminal via a UART peripheral built with the same process (VHDL, Avalon interface, Nios II integration), with commands to configure scan range and speed.
Added an IP to drive a 12-LED NeoPixel ring (WS2812 protocol) to animate the radar, also integrated as an Avalon peripheral.
Results & Deliverables
- End-to-end 2D mapping system: sensor → embedded Nios II processing → real-time VGA display
- Two original hardware IPs (ultrasonic rangefinder, servo motor) designed, simulated, then integrated as custom Avalon peripherals
- Radar data exported to a PC terminal over UART, with remotely configurable scan parameters
- All 6 steps of the assignment completed, including the bonus UART and NeoPixel LED animation parts
Visuals & Waveforms
Visuals coming soon.