VHDL Single-Cycle Processor Architecture
- VHDL
- ModelSim
- Quartus
- FPGA (DE1-SOC)
- UART
- Interrupts (VIC)
Engineering project completed at Polytech Sorbonne: full design of a 32-bit single-cycle processor in VHDL, from the core datapath up to an interrupt-driven UART peripheral, validated in simulation and implemented on hardware.
Design of a 32-bit single-cycle processor inspired by the ARM instruction set, split into three units: the datapath (32-bit ALU, 16-register file, data memory), the instruction fetch unit (program counter, instruction memory, sign extension) and the control unit (combinational instruction decoder, PSR status register).
Each block was described in behavioral VHDL and independently validated with dedicated ModelSim testbenches before assembling the full processor, with cycle-by-cycle verification of a test program (memory summation loop, conditional branches).
Added a vectored interrupt controller (VIC) handling two prioritized IRQ sources, with context save/restore in the interrupt service routine (link register LR) and a dedicated return instruction (BX).
Developed a UART peripheral (transmit and receive) integrated into the processor through memory-mapped address decoding, sending a character string to a PC terminal, with interrupt-driven transmission to respect baud rate timing.
Final implementation on an Intel MAX 10 FPGA (DE10-Lite): synthesis in Quartus, pin assignment, program result displayed on 7-segment displays, and serial communication validated through a USB/UART converter.
Results & Deliverables
- Fully working processor in simulation and on FPGA, executing a simplified ARM instruction set (arithmetic, logic, conditional branches, memory access)
- Hardware interrupt handling validated with context save/restore and two-source IRQ prioritization
- End-to-end UART serial link, from the VHDL-generated Tx signal to reception on a PC terminal
- Validated at every stage with dedicated ModelSim testbenches before each hardware implementation
Visuals & Waveforms
